HP OpenVMS Calling Standard

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Index

A.4.3.1 General Information Segment

The OpenVMS general information segment contains various flags and general exception handling information, and is described in Table A-14.

A general information segment may be omitted if all of its fields would have their default values.

If a general information segment is present, it must be the first segment in the operating system-specific data area.

Table A-14 Operating System-Specific Data Area
Field Bit Position Description

OSSD$V_TYPE <14:0> A 15-bit type field that identifies the segment as a general information segment. The value of this field is OSSD$K_GENERAL_INFO (=1).

OSSD$V_S <15> If set to 1, another segment immediately follows this one. If set to 0, there are no further segments in this area.

OSSD$V_EXCEPTION_MODE <18:16> A 3-bit field that encodes the caller's desired exception-reporting behavior when calling certain mathmatically oriented library routines. These routines generally search up the call stack to find the desired exception behavior whenever an error is detected. However, if no floating-point exceptions are enabled in the I64 FPSR, then no stack search is performed and the exception mode SIGNAL_SILENT is assumed ¹.

Value Name Meaning

0 OSSD$K_EXC_MODE_SIGNAL Raise exceptions for all error conditions except for underflows producing a 0 result. This is the default mode.

1 OSSD$K_EXC_MODE_SIGNAL_ALL Raise exceptions for all error conditions (including underflows).

2 OSSD$K_EXC_MODE_SIGNAL_SILENT Raise no exceptions. Create only finite values (no infinities, denormals, or NaNs). In this mode, either the function result or the C language errno variable must be examined for any error indication.

3 OSSD$K_EXC_MODE_FULL_IEEE Raise no exceptions except as controlled by separate IEEE exception enable bits. Create infinities, denormals, or NaN values according to the IEEE floating-point standard.

4 OSSD$K_EXC_MODE_CALLER Perform the exception-mode behavior specified by this procedure's caller.

OSSD$V_TARGET_INVO <19> If set to 1, the exception handler for this procedure is invoked when this procedure is the target invocation of an unwind. Note that a procedure is the target invocation of an unwind if it is the procedure in which execution resumes following completion of the unwind. The default value is 0.

OSSD$V_BASE_FRAME <20> This bit must be zero except in operating system routines whose documented purpose is to provide the base frame marker. If set to 1, this bit indicates the logical base frame of a stack that precedes all frames corresponding to user code. The interpretation and use of this frame and whether there are any predecessor frames is system software defined (and subject to change). The default value is 0.

OSSD$V_HANDLER_REINVOKABLE <21> If set to 1, the handler can be reinvoked, allowing an occurrence of another exception while the handler is already active. If this bit is set to 0, the exception handler cannot be reinvoked. The default value is 0.

OSSD$V_AST_FRAME <22> If set to 1, then this is an AST dispatch frame. The interrupted procedure is the predecessor frame on the stack and much of its context is saved in this procedure's memory stack frame. The default value is 0.

OSSD$V_EXCEPTION_FRAME <23> If set to 1, then this is an exception dispatch frame. The excepting procedure is the predecessor frame on the stack and much of its context is saved in this procedure's memory stack frame. The default value is 0.

OSSD$V_TIE_FRAME <24> If set to 1, this is a frame created by the Translated Image Executive for use during the execution of translated images. The default value is 0.

OSSD$V_BOTTOM_OF_STACK <25> A value of 1 indicates that this frame has no predecessor frames (that is, this frame is the end of the invocation call chain). The default value is 0.

OSSD$V_HANDLER_DATA_VALID <26> A value of 1 indicates that an exception handler data field is present in the unwind information block. The default value is 0.

OSSD$V_SS_DISPATCH_FRAME <27> If set to 1, then this is the System Service dispatch frame. Much of the context for a procedure calling a system service is saved on an inner mode stack. The default value is 0.

OSSD$V_KP_START_FRAME <28> Internal use only.

OSSD$V_FRAMELESS_HELPER <29> Tags code executing in context of another routine whose IP is in B0

RESERVED <63:30> Reserved; must be zero.

¹This is different than on Alpha, where a stack search is performed even when no floating-point exceptions are enabled in the Alpha FPCR (see the description of PDSC$V_EXCEPTION_MODE in Table 3-3 and Table 3-4.)

A.4.3.2 Caller Spill Register Information

The OpenVMS caller spill register information segment encodes information to emulate the effects of callee register saving conventions even when caller save/restore conventions are in use. The key difference between this and the more general unwind information described in other parts of Section A.4 is that the information described here must be applied in the frame with which it is associated in order to complete that frame whereas other information is applied in order to unwind to the previous frame.

The caller spill register segment is described in Table A-15.

Table A-15 OpenVMS OSSD Caller Spill Register Information
Field Bit Position Description

OSSD$V_TYPE <14:0> A 15-bit type field that identifies the segment as a caller spill register information segment. The value of this field is OSSD$K_CALLER_SPILL_INFO (=2).

OSSD$V_S <15> If set to 1, another segment immediately follows this one. If set to 0, there are no further segments in this area.

OSSD$W_LENGTH <31:16> A two-byte field that specifies the number of quadwords in this segment (including OSSD$V_TYPE, OSSD$V_S and OSSD$W_LENGTH itself).

OSSD$T_SPILL_DATA <...> See below.

**Table A-15 OpenVMS OSSD Caller Spill Register Information**
Field	Bit Position	Description
OSSD$V_TYPE	<14:0>	A 15-bit type field that identifies the segment as a caller spill register information segment. The value of this field is OSSD$K_CALLER_SPILL_INFO (=2).
OSSD$V_S	<15>	If set to 1, another segment immediately follows this one. If set to 0, there are no further segments in this area.
OSSD$W_LENGTH	<31:16>	A two-byte field that specifies the number of quadwords in this segment (including OSSD$V_TYPE, OSSD$V_S and OSSD$W_LENGTH itself).
OSSD$T_SPILL_DATA	<...>	See below.

The OSSD$T_SPILL_DATA field in a spill register segment consists of a sequence of triples encoded as shown in Figure A-3.

Figure A-3 Format of OSSD$T_SPILL_DATA

Table A-16 describes the fields in the OSSD$T_SPILL_DATA segment.

Table A-16 Description of OSSD$T_SPILL_DATA Segment
OSSD$V_REG A 5-bit field that identifies the saved static general register. Bits <7:5> of byte 0 are reserved and must be zero.
A REG value of zero indicates that there is no more spill data; one or more zero bytes are used to pad the end of the spill data if needed to fill out the specified length.

OSSD$V_TREG A 7-bit field that identifies one of the general registers. Bit <7> of byte 1 is reserved and must be zero.
A TREG value other than zero indicates that the contents of register REG is saved in register TREG. A TREG value of zero indicates that register REG is restored, that is, is no longer saved elsewhere.

OSSD$T_T A ULEB128 slot offset from the start address given in the corresponding unwind table (see Section A.4.1) to the instruction that performs the save or restore.
It is valid for save actions to occur in a prologue and restore events to occur in an epilogue. (Save actions events will never occur in an epilogue and restore events will never occur in an prologue because these would require a call to occur in either the prologue or epilogue, which is forbidden.)

**Table A-16 Description of OSSD$T_SPILL_DATA Segment**
OSSD$V_REG	A 5-bit field that identifies the saved static general register. Bits <7:5> of byte 0 are reserved and must be zero. A REG value of zero indicates that there is no more spill data; one or more zero bytes are used to pad the end of the spill data if needed to fill out the specified length.
OSSD$V_TREG	A 7-bit field that identifies one of the general registers. Bit <7> of byte 1 is reserved and must be zero. A TREG value other than zero indicates that the contents of register REG is saved in register TREG. A TREG value of zero indicates that register REG is restored, that is, is no longer saved elsewhere.
OSSD$T_T	A ULEB128 slot offset from the start address given in the corresponding unwind table (see Section A.4.1) to the instruction that performs the save or restore. It is valid for save actions to occur in a prologue and restore events to occur in an epilogue. (Save actions events will never occur in an epilogue and restore events will never occur in an prologue because these would require a call to occur in either the prologue or epilogue, which is forbidden.)

It is valid for two or more save actions for the same register REG to occur without an intervening restore of that register. In this case, the later save register location TREG supercedes the earlier one as the save location for register REG beginning at the specified offset T.

When unwinding to a frame, the unwind information of the called frame is first used to construct the frame of the caller; the unwind operation must then be completed by using any spill register information for that caller.

A.4.4 Language-Specific Data Area

The language-specific data area contains information whose format and interpretation need be known only by the condition handler that uses it. As such, this area is not described in this document.

To preserve sharability of the image of which language-specific data is a part, that data should be read-only and position-independent. For example, an address within the associated procedure might be represented as an offset relative to the starting address given in the unwind table for the routine.

The following fields, which are found in the mechanism vector passed to a condition handler (see Sections 8.5.1 and 8.5.1.2.3), may be helpful in interpreting the contents of language-specific data:

CHF$PH_MCH_UWR_START The virtual address of an unwind region. May be used together with an offset in the language specific data to encode an address within a procedure.

CHF$PH_MCH_DADDR The virtual address of the language-specific data area.

A.5 Default Unwind Information

A null frame procedure may have no corresponding unwind table entry, hence no unwind information block, if all of the following apply:

It has no memory stack, no register stack and preserves no context of its caller (these are properties of all null frame procedures), hence requires no unwind descriptors. Note in particular that this means that B0 and AR.PFS are unchanged throughout the execution of the procedure. (See Sections A.4 and A.4.4.)
It has no condition handler, hence also no language-specific data area. (See Sections 4.4 and A.4.4.)
It has no operating system-specific data area. (See Section A.4.3.)

Such a procedure is necessarily a leaf procedure, that is, a procedure that makes no calls, either explicitly or implicitly. (To make a call, a procedure must preserve at least B0 and AR.PFS.)

Conversely, if the dispatcher or unwinder encounters a PC for the top-most procedure on the call stack that is not represented in the unwind tables, it assumes that the PC corresponds to a null frame leaf procedure that satisfies the properties described above.

A.6 System Unwind Routines

See the HP OpenVMS System Services Reference Manual for descriptions of the following unwind routines:

SYS$SET_UNWIND_TABLE
SYS$CLEAR_UNWIND_TABLE
SYS$GET_UNWIND_ENTRY_INFO

See the HP OpenVMS RTL Library (LIB$) Manual for a decription of the following routine:

LIB$GET_UIB_INFO

Appendix B
Unwind Descriptor Record Format

Note

For compatibility with the VAX and Alpha calling standards, this appendix describes big-endian values stored in little-endian bytes.

The unwind descriptor records are encoded in variable-length byte strings. The various record formats are described in this appendix. The first byte of each record is sufficient to determine its format. The high-order bit of this byte determines whether it is a header record (if the bit is zero), or a region descriptor record (if the bit is one). The remaining bits and any subsequent bytes are divided into separate fields. In most formats, the first field, R, identifies the record type. The record formats are listed by the bit pattern of the first byte in Table B-1.

Table B-1 Record Formats
Region Header Records Prologue Descriptor Records Body Descriptor Records

Bit Pattern Format Bit Pattern Format Bit Pattern Format

00-- ---- R1 100- ---- P1 10-- ---- B1

0100 0--- R2 1010 ---- P2

0110 00-- R3 1011 0--- P3

1011 1000 P4

1011 1001 P5

110- ---- P6 110- ---- B2

1110 ---- P7 1110 0000 B3

1111 0000 P8 1111 -000 B4

1111 0001 P9

1111 1001 X1 1111 1001 X1

1111 1010 X2 1111 1010 X2

1111 1011 X3 1111 1011 X3

1111 1100 X4 1111 1100 X4

1111 1111 P10

**Table B-1 Record Formats**
Region Header Records	Prologue Descriptor Records	Body Descriptor Records
Bit Pattern	Format	Bit Pattern	Format	Bit Pattern	Format
`00-- ----`	R1	`100- ----`	P1	`10-- ----`	B1
`0100 0---`	R2	`1010 ----`	P2
`0110 00--`	R3	`1011 0---`	P3
		`1011 1000`	P4
		`1011 1001`	P5
		`110- ----`	P6	`110- ----`	B2
		`1110 ----`	P7	`1110 0000`	B3
		`1111 0000`	P8	`1111 -000`	B4
		`1111 0001`	P9
		`1111 1001`	X1	`1111 1001`	X1
		`1111 1010`	X2	`1111 1010`	X2
		`1111 1011`	X3	`1111 1011`	X3
		`1111 1100`	X4	`1111 1100`	X4
		`1111 1111`	P10

Some fields in the unwind descriptor records are variable in length. The variable-length encoding uses the ULEB128 (Unsigned Little-Endian Base 128) encoding, described below:

Divide the number into groups of 7 bits, beginning at the low-order end.
Discard all groups of leading zeroes, but keep at least the first (low-order) group if the number is all zeroes.
Place a 1 bit to the left of of all but the last group; place a 0 bit to the left of the last group. This forms one or more 8-bit groups.

Table B-2 shows example ULEB128 encodings.

Table B-2 Example ULEB128 Encodings
Value Encoding Interpretation

0 00000000 0

127 01111111 127

128 10000000
00000001 0 + (1 << 7)

1544 10001000
00001100 8 + (12 << 7)

49,802 10001010
10000101
00000011 10 + (5 << 7) + (3 << 14)

**Table B-2 Example ULEB128 Encodings**
Value	Encoding	Interpretation
0	`00000000`	0
127	`01111111`	127
128	`10000000` `00000001`	0 + (1 << 7)
1544	`10001000` `00001100`	8 + (12 << 7)
49,802	`10001010` `10000101` `00000011`	10 + (5 << 7) + (3 << 14)

Fields in the ULEB128 format always follow the fixed fields, and begin on a byte boundary.

B.1 Region Header Records

The PROLOGUE and BODY region header records can appear in either format R1 or R3, depending on the magnitude of the region length field. If the region length is no greater than 31 instruction slots, the R1 format may be used; otherwise, format R3 must be used.

B.1.1 Format R1

This format is used for the short forms of the PROLOGUE and BODY region header records. The R bit identifies the record type, as shown in the following table:

Record Type R

PROLOGUE 0

BODY 1

Record Type	R
PROLOGUE	0
BODY	1

B.1.2 Format R2

This format is used only for the PROLOGUE_GR region header record. The following table shows the meaning of the bits in the MASK field:

Mask bit Meaning when bit is set

Byte 0, bit 2 RP is saved in a standard general register.

Byte 0, bit 1 AR.PFS is saved in a standard general register.

Byte 0, bit 0 PSP is saved in a standard general register.

Byte 1, bit 7 Predicate registers are saved in a standard general register.

Mask bit	Meaning when bit is set
Byte 0, bit 2	RP is saved in a standard general register.
Byte 0, bit 1	AR.PFS is saved in a standard general register.
Byte 0, bit 0	PSP is saved in a standard general register.
Byte 1, bit 7	Predicate registers are saved in a standard general register.

The GRSAVE field identifies the general register in which the first of these values is stored. Additional general registers are used as needed. For example, assume that RP, AR.PFS, and the predicate registers are stored, but not PSP. The mask bits would be 1101, and GRSAVE might be set to 39, indicating that the three values are stored in R39, R40, and R41, respectively.