Continues program execution following a breakpoint.

Format

;P

Description

The Proceed from Breakpoint command continues program execution at the address contained in the PC of the program. Program execution continues until the next breakpoint or until program completion.

Note If DELTA/XDELTA does not have write access to the target of a JSR instruction, you cannot use the S or ;P command at the JSR instruction. First, you must use the O command; then you can use the S or ;P command.

The following examples illustrate the command on each OpenVMS platform.

Example

I64 example:

G0BF5D60,0;X (1) G0BF5D60 X0+60;B 1 00000060 (2) ;P (3) Brk 1 at X0+00000060 on CPU 0 (4) X0+00000060! alloc r53 = ar.pfs, 18, 08, 00 (New IPL = 0) - (New mode = USER)

1. Set the base register.
2. Set a breakpoint at address X0+00000060 using ;B.
3. Program execution is continued using the ;P command.
4. Program execution halts at breakpoint 1. DELTA/XDELTA displays the breakpoint message (the breakpoint number and the address) and the instruction.

Alpha example:

;B 1 00030010 (1) ;P (2) Brk 1 at 00030010 00030010! STQ R26,#X0008(SP) (3)

1. Current breakpoints are displayed using ;B (breakpoint 1 at address 30010).
2. Program execution is continued using the ;P command.
3. Program execution halts at breakpoint 1. DELTA/XDELTA displays the breakpoint message (the breakpoint number and the address) and the instruction.

VAX example:

;B 2 00000699 (1) ;P (2) 2 BRK AT 00000699 00000699/BSBB 000006A2 (3)

1. Current breakpoints are displayed using ;B (breakpoint 2 at address 699).
2. Program execution is continued using the ;P command.
3. Program execution halts at breakpoint 2. DELTA/XDELTA displays the breakpoint message (the breakpoint number and the address) and the instruction.

Analyzes absolute and self-relative longword queues and displays the results of the analysis.

Format

queue_header_address[,queue_type];Q

Argument

queue_header_address

The queue header must be at least longword aligned.

queue_type

A queue type of zero (the default) represents an absolute queue. A queue type of 1 indicates a self-relative queue.

Description

The validate queue function is similar to the one in the OpenVMS System Dump Analyzer Utility. It can analyze both absolute and self-relative longword queues and display the results of the analysis. This function identifies various problems in the queue headers and invalid backward links for queue entries and evaluates the readability of both. For valid queues, it tells you the total number of entries. For invalid queues, it tells you the queue entry number and the address that is invalid and why.

Example

FFFFFFFF8000F00D;Q !Absolute at GF00D GF00D,0;Q !Absolute at GF00D GF00,1;Q !Self-relative at GF00

XDELTA only; displays contents of an interrupt stack frame.

Format

addr_exp ;T

Parameters

addr-exp

The address of the stack frame. This is an optional argument. If not specified, the ;T command without any argument displays the interrupt stack frame with which XDELTA was invoked.

Description

On I64 systems, the XDELTA ;T command displays the contents of an interrupt stack frame.

Example

In the following example, the ;T command displays the machine state at the time of the exception.

;T * Exception Frame Display: * Exception taken at IP FFFFFFFF.8063D830, slot 01 from Kernel mode Exception Frame at FFFFFFFF.89DA1CE0 Trap Type 00000080 (External Interrupt) IVT Offset 00003000 (External Interrupt) External Interrupt Vector 00000000 * = Value read directly from the register rather than the frame Control Registers: CR0 Default Control Register (DCR) 00000000.00007F00 CR1 Interval Timer Match Register (ITM) * 0000C6F7.31F82D5B CR2 Interruption Vector Address (IVA) * FFFFFFFF.801D0000 CR8 Page Table Address (PTA) * FFFFFFFF.7FFF013D CR16 Processor Status Register (IPSR) 00001210.0A026010 CR17 Interrupt Status Register (ISR) 00000200.00000000 CR19 Instruction Pointer (IIP) FFFFFFFF.8063D830 CR20 Faulting Address (IFA) FFFFFFFF.88580078 CR21 TLB Insertion Register (ITIR) 00000000.00000334 CR22 Instruction Previous Address (IIPA) FFFFFFFF.8063D830 CR23 Function State (IFS) 80000000.00000FA7 CR24 Instruction immediate (IIM) FFFFFFFF.88580078 CR25 VHPT Hash Address (IHA) FFFFFFFF.7FFF5860 CR64 Local Interrupt ID (LID) * 00000000.00000000 CR66 Task Priority Register (TPR) * 00000000.00010000 CR68 External Interrupt Req Reg 0 (IRR0) * 00000000.00000000 CR69 External Interrupt Req Reg 1 (IRR1) * 00000000.00000000 CR70 External Interrupt Req Reg 2 (IRR2) * 00000000.00000000 CR71 External Interrupt Req Reg 3 (IRR3) * 00020000.00000000 CR72 Interval Time Vector (ITV) * 00000000.000000F1 CR73 Performance Monitoring Vector (PMV) * 00000000.000000FB CR74 Corrected Machinecheck Vector (CMCV) * 00000000.00010000 CR80 Local Redirection Register 0 (LRR0) * 00000000.00010000 CR81 Local Redirection Register 1 (LRR1) * 00000000.00010000 Application Registers: AR0 Kernel Register (KR0) * 00000000.20570000 AR1 Kernel Register (KR1) * 00000000.60000000 AR2 Kernel Register (KR2) * 00000000.00000000 AR3 Kernel Register (KR3) * 00000000.00000000 AR4 Kernel Register (KR4) * 00000000.00000000 AR5 Kernel Register (KR5) * 0000C6F7.31F82D5B AR6 Kernel Register (KR6) * FFFFFFFF.84C3E000 AR7 Kernel Register (KR7) * FFFFFFFF.89D4B000 AR16 Register Stack Config Reg (RSC) 00000000.00000000 AR17 Backing Store Pointer (BSP) FFFFF802.A3EAC300 AR18 Backing Store for Mem Store (BSPSTORE) FFFFF802.A3EAC300 AR19 RSE NaT Collection Register (RNAT) 00000000.00000000 AR32 Compare/Exchange Comp Value Reg (CCV) FFFFFFFF.84132680 AR36 User NaT Collection Register (UNAT) 00000000.00000000 AR40 Floating-point Status Reg (FPSR) 0009804C.0270033F AR44 Interval Time Counter (ITC) * 0000C6FB.A91997B5 AR64 Previous Function State (PFS) 00000000.00000FA7 AR65 Loop Count Register (LC) 00000000.00000000 AR66 Epilog Count Register (EC) 00000000.00000000 Processor Status Register (IPSR): AC = 0 MFL= 1 MFH= 0 IC = 1 I = 1 DT = 1 DFL= 0 DFH= 0 RT = 1 CPL= 0 IT = 1 MC = 0 RI = 1 Interrupt Status Register (ISR): Code 00000000 X = 0 W = 0 R = 0 NA = 0 SP = 0 RS = 0 IR = 0 NI = 0 SO = 0 EI = 1 ED = 0 Branch Registers: Region Registers: B0 FFFFFFFF.8063C570 RR0 * 00000000.00000035 B1 00000000.00000000 RR1 * 00000000.00000030 B2 00000000.00000000 RR2 * 00000000.00000030 B3 00000000.00000000 RR3 * 00000000.00000030 B4 00000000.00000000 RR4 * 00000000.00000030 B5 00000000.00000000 RR5 * 00000000.00000030 B6 FFFFFFFF.80001580 RR6 * 00000000.00000030 B7 FFFFFFFF.806F4D30 RR7 * 00000000.00000335 Floating Point Registers: FPSR 0009804C.0270033F F6 00000000.0001003E.00000000.0000FCBE F7 00000000.0001003E.00000000.00000040 F8 00000000.0001003E.00000000.003F2F80 F9 00000000.00010003.80000000.00000000 F10 00000000.0000FFFB.80000000.00000000 F11 00000000.0000FFFB.80000000.00000000 Miscellaneous Registers: Processor Identifier (CPUID 0,1) GenuineIntel (CPUID 3) 00000000.1F010504 Interrupt Priority Level (IPL) 00000003 Stack Align 000002D0 NaT Mask 001C PPrev Mode 00 Previous Stack 00 Interrupt Depth 00 Preds 00000000.FF65CCA3 Nats 00000000.00000000 Context 00000000.FF61CEA3 General Registers: R0 00000000.00000000 GP FFFFFFFF.8442E200 R2 FFFFFFFF.84132688 R3 FFFFFFFF.8442E200 R4 FFFFFFFF.8442E200 R5 00000000.00000001 R6 FFFFFFFF.84C3E000 R7 00000000.00000000 R8 00000000.00000003 R9 00000000.00000009 R10 00000000.00000008 R11 00000000.00000000 SP FFFFFFFF.89DA0D18 TP 00000000.00000000 R14 00000000.00000001 R15 FFFFFFFF.8401BD90 R16 FFFFFFFF.84017508 R17 FFFFFFFF.84009E98 R18 FFFFFFFF.84C3F274 R19 00000000.00000000 R20 FFFFFFFF.84009E00 R21 FFFFFFFF.84132627 R22 FFFFFFFF.84C3E01C R23 00000000.0000000F R24 00000000.00011F90 R25 00000000.00000003 R26 00000000.00000000 R27 FFFFFFFF.84132668 R28 FFFFFFFF.8416D7C8 R29 FFFFFFFF.89DA1FB0 R30 00000000.7FF2E318 R31 00000000.00000000 Interrupted Frame RSE Backing Store , Size = 39 registers FFFFF802.A3EAC300: FFFFFFFF.84C3E080 (R32) FFFFF802.A3EAC308: E0000000.00000000 (R33) FFFFF802.A3EAC310: FFFFFFFF.84132628 (R34) FFFFF802.A3EAC318: FFFFFFFF.88598080 (R35) FFFFF802.A3EAC320: 00000000.00000001 (R36) FFFFF802.A3EAC328: FFFFFFFF.806029A0 (R37) FFFFF802.A3EAC330: 00000000.FF65C563 (R38) FFFFF802.A3EAC338: 00000000.00000000 (R39) FFFFF802.A3EAC340: FFFFFFFF.8442E200 (R40) FFFFF802.A3EAC348: FFFFFFFF.806029C0 (R41) FFFFF802.A3EAC350: FFFFFFFF.8442E200 (R42) FFFFF802.A3EAC358: FFFFFFFF.88598080 (R43) FFFFF802.A3EAC360: FFFFFFFF.84191000 (R44) FFFFF802.A3EAC368: 00000000.00000009 (R45) FFFFF802.A3EAC370: FFFFFFFF.8416D7C8 (R46) FFFFF802.A3EAC378: FFFFFFFF.8442E200 (R47) FFFFF802.A3EAC380: 00000000.00000000 (R48) FFFFF802.A3EAC388: FFFFFFFF.84132668 (R49) FFFFF802.A3EAC390: 00000000.00000008 (R50) FFFFF802.A3EAC398: 00000000.00000000 (R51) FFFFF802.A3EAC3A0: 00000000.7FF2E318 (R52) FFFFF802.A3EAC3A8: 00000000.00000000 (R53) FFFFF802.A3EAC3B0: 00000000.00000FB2 (R54) FFFFF802.A3EAC3B8: FFFFFFFF.84132627 (R55) FFFFF802.A3EAC3C0: 00000000.00000003 (R56) FFFFF802.A3EAC3C8: FFFFFFFF.89DA1FB0 (R57) FFFFF802.A3EAC3D0: FFFFFFFF.801D9BD0 (R58) FFFFF802.A3EAC3D8: FFFFFFFF.806029C0 (R59) FFFFF802.A3EAC3E0: 00000000.00000001 (R60) FFFFF802.A3EAC3E8: FFFFFFFF.89DA1FB0 (R61) FFFFF802.A3EAC3F0: FFFFFFFF.8442E200 (R62) FFFFF802.A3EAC400: 00000000.00000003 (R63) FFFFF802.A3EAC408: FFFFFFFF.8063C570 (R64) FFFFF802.A3EAC410: 00000000.00000008 (R65) FFFFF802.A3EAC418: 00000000.00000008 (R66) FFFFF802.A3EAC420: FFFFFFFF.84132668 (R67) FFFFF802.A3EAC428: FFFFFFFF.8416D7C8 (R68) FFFFF802.A3EAC430: 00000000.00000008 (R69) FFFFF802.A3EAC438: FFFFFFFF.8416DAA0 (R70)

Lists information about an image that contains the address you supplied.

Format

address-expression;W

sequence number, offset;W

Arguments

address-expression

An address contained within an executive image or a user image.

sequence number

The identifier assigned to an executive image.

offset

The distance from the base address of the image.

Description

The ;W command is used for debugging code that resides in system or user space. You can use this command with XDELTA for debugging an executive image. You can also use this command with DELTA.

To examine the executive image list, you must be running in executive mode or your process must have change-mode-to-executive (CMEXEC) privilege.

This command can be used in two ways. In the first way, if you supply an address that you are trying to locate, the command lists the name of the executive or user image that contains the address, its base and ending addresses, and the offset of the address from the base of the image. For any executive image that has been sliced, it also displays its sequence number. The offset can be used with the link map of the image to locate the actual code or data. This offset is saved in the value Q.

In the second way, if you supply the sequence number of a sliced executive image and an offset, the command computes and displays the address in memory. The address is saved in the value Q.

Examples

The first form of the command takes a system space address as a parameter and attempts to locate that address within the loaded executive images. This command works for both sliced and unsliced loadable executive images. The output is very similar to ;L, except the offset is displayed for you, as shown in the following example:

80026530;W Seq# Image Name Base End Image Offset 000C SYSTEM_SYNCHRONIZATION.EXE Nonpaged read only 80024000 8002C800 00002530

The second form of the command takes a loadable executive image sequence number and an image offset from the map file as parameters. The output, again, is very similiar to ;L, except that the system space address that corresponds to the image offset is displayed, as shown in the following example:

C,2530;W Seq# Image Name Base End Address 000C SYSTEM_SYNCHRONIZATION.EXE Nonpaged read only 80024000 8002C800 80026530

Places an address in a base register.

Format

address-expression,n[,y];X

Arguments

address-expression

The address to place in the base register.

n

The number of the base register.

y

On I64 and Alpha, a parameter for modifying the default offset of 10000₁₆. The valid range is 1 to FFFFFFFF.

Description

On I64 and Alpha, to place an address in a base register, enter:

• An expression followed by a comma (,), or
• A number from 0 to 15₁₀, or optionally, a number from 1 to FFFFFFFF, a semicolon (;)
• The letter X.

On VAX, to place an address in a base register, enter an expression followed by a comma (,), a number from 0 to F₁₆, a semicolon (;), and the letter X.

On all platforms, DELTA/XDELTA places the address in the base register. DELTA/XDELTA confirms that the base register is set by displaying the value deposited in the base register.

For example, the following command places the address 402 in base register 0. DELTA/XDELTA then displays the value in the base register to verify it.

402,0;X [Return] 00000402

Whenever DELTA/XDELTA displays an address, it will display a relative address if the address falls within the computer's valid range for an offset from a base register. The relative address consists of the base register identifier (Xn), followed by an offset. The offset gives the address location in relation to the address stored in the base register.

For example, if base register 2 contains 800D046A, the address that would be displayed is X2+C4, the base register identifier followed by the offset.

Relative addresses are computed for both opened and displayed locations and for addresses that are instruction operands.

If you have defined several base registers, the offset will be relative to the closest base register. If an address falls outside the valid range, it is displayed as a hexadecimal value.

On I64, the default offset is 100000₁₆, which can be modified.

On Alpha, the default offset is 10000₁₆, which can be modified.

On VAX, the default offset is 2000₁₆ bytes. It cannot be modified.

The following examples illustrate the command on each platform.

Examples

I64 example:

G0BF5D60,0,200;X 1 ;X 0 80BF5D60 00000200 4 8392A900 5 83009DE0 13 FFFFF802 06C00000 14 830937F0 15 83093700 G0BF5D60,0,200;X (1) ;X 0 80BF5D60 00000200 4 8392A900 5 83009DE0 13 FFFFF802 06C00000 14 830937F0 15 83093700 (2)

1. Set the base register, with an offset.
2. The ;X command with no arguments displays the existing base register values. Offset values are also displayed, if their value is other than the default offset.

Alpha example:

30000,0;X (1) 00030000 30070,1,200;X (2) 00030070 ;X (3) 0 00030000 1 00030070 00000200 S (4) X0+00000004! BIS R31,R31,R18 x1+10! STQ FP,#X0020(SP) (5)

1. The base address of the program (determined from the map file) is virtual address 30000. The base address is stored in base register 0 with ;X, using the default offset. DELTA/XDELTA displays the value in base register 0 just loaded, 30000.
2. The address of a subroutine, 30070, is stored in base register 1, specifying a new offset of 200 (to override the default value of 100000). Note that this command could also have been expressed as "x0+70,1,200;X". DELTA/XDELTA displays the value in base register 1 just loaded, 30070.
3. The ;x command is used to display the current base registers. Note that for those not using the default offset, the offset is also displayed.
4. The S command is used to execute the first instruction in the main routine. DELTA/XDELTA displays the address of the next instruction, 30004, as x0+00000004 and then displays the instruction at that address.
5. The instruction at offset 10 from base register 1 is displayed in instruction mode using the ! command.

VAX example:

00000664/CLRQ -(SP) 200,1;X (1) 00000200 (2) X1 490!CMPL R0,#000009A8 (3) X1 499!BSBB X1+04A2 (4)

1. The base address of the program (determined from the map file) is virtual address 200. The base address is stored in base register 1 with ;X.
2. DELTA/XDELTA displays the value in base register 1 just loaded, 200.
3. The instruction at offset 490 is displayed in instruction mode using the ! command. The address reference is X1+490 (the + sign is implied when not specified). DELTA/XDELTA displays the instruction at address X1+490.
4. The instruction at offset 499 is displayed. This instruction is a branch instruction. DELTA/XDELTA displays the address of the branch in offset notation.

Executes one instruction, steps over a subroutine by executing it, and displays the instruction to which the subroutine returns control.

Format

O

Description

The Step Instruction over Subroutine command executes one instruction and displays the address of the next instruction. If the instruction executed is a call to a subroutine, the subroutine is executed and the next instruction displayed is the instruction to which the subroutine returns control. Use this command to do single-step instruction execution excluding single-stepping of instructions within subroutines. If you want to do single-step execution of all instructions, including those in subroutines, use the S command.

This command sets a flag to change the display mode to instruction mode. Any subsequent Close Current Location, Open Next (LINEFEED) commands and Open and Display Indirect Location (TAB) commands will display locations as machine instructions. The Open Location and Display Contents (/) command clears the flag, causing the display mode to revert to longword, hexadecimal mode.

On I64, the subroutine call instruction is br.call.

On Alpha, the subroutine call instructions are JSR and BSR.

On VAX, the subroutine call instructions are BSBB, BSBW, JSB, CALLG, and CALLS.

On all platforms, if you set a breakpoint in the subroutine and enter the O command, program execution breaks at the subroutine breakpoint. When you enter a Proceed command (;P), and program execution returns to the instruction to which the subroutine returns control, a message is displayed, as follows:

On I64 and Alpha systems:

Step-over at nnnnnnnn instruction

On VAX systems:

STEPOVER BRK AT nnnnnnnn instruction

The message informs you that program execution has returned from a subroutine.

If you are using XDELTA in a multiprocessor environment, the CPU ID of the processor where the break was taken is also displayed.

On I64 and Alpha, the CPU ID is displayed as a decimal number with no leading zeros.

On VAX, the CPU ID is displayed as a 2-digit hexadecimal number.

The following examples illustrate the command on each OpenVMS platform.

Examples

I64 example:

X0+00000380! mov r7 = r23S (1) X0+00000381! nop.f 000000S X0+00000382! br.call.sptk.many b0 = 0000E30 O (2) X0+00000390! mov r29 = r41S (3) X0+00000391! mov r1 = r40S

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