HP OpenVMS Calling Standard

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5.1.3 Signature Information Fields in Function Descriptors

The signature information field of the function descriptor is encoded using the low three bits of the field as a tag that specifies the interpretation of the rest of the field. Table 5-1 contains the meaning of the values specified by the tag value.

Table 5-1 Signature Information Field Tag Values
Tag Value
(low 3 bits) Meaning

0 The signature information field as a whole (including the tag bits) is the address of a signature information block (see Section 5.2). However, if the address is null, no signature information is available.

1 Default signature information applies, which is based on the information in the argument information register (see Section 5.2.5). In this case the rest of the field must be zero.

2 The field as a whole is a signature information block (see Section 5.2) that is immediately contained in the function descriptor. This can only be used for a signature information block whose size is less than or equal to 64 bits (which can represent up to 12 arguments).

3---7 Reserved.

**Table 5-1 Signature Information Field Tag Values**
Tag Value (low 3 bits)	Meaning
0	The signature information field as a whole (including the tag bits) is the address of a signature information block (see Section 5.2). However, if the address is null, no signature information is available.
1	Default signature information applies, which is based on the information in the argument information register (see Section 5.2.5). In this case the rest of the field must be zero.
2	The field as a whole is a signature information block (see Section 5.2) that is immediately contained in the function descriptor. This can only be used for a signature information block whose size is less than or equal to 64 bits (which can represent up to 12 arguments).
3---7	Reserved.

5.2 Signature Information Blocks

Signature information blocks on Alpha and I64 systems are nearly identical in content and interpretation. However, they differ in the following ways:

Signature information blocks are associated with the corresponding Alpha procedure descriptor or I64 function descriptor differently (see Section 5.1).
Signature information fields are arranged in different orders.
An I64 signature information block includes control information that is not present in an Alpha signature information block (see Section 5.1.3).

5.2.1 Signature Information on Alpha Systems

If a procedure is compiled with signature information, PDSC$W_SIGNATURE_OFFSET contains a byte offset from the procedure descriptor to the start of a signature information block. The maximum size of the signature information block is 72 bytes (defined by constant PSIG$K_MAX_SIZE). The fields defined in the signature information block are illustrated in Figure 5-1 and described in Table 5-2.

Figure 5-1 Alpha Signature Information Block (PSIG)

5.2.2 Signature Information on I64 Systems

Signature information is represented in Figure 5-2, and is explained in Table 5-2, Table 5-3, and Table 5-4.

Signature information is defined only for standard calls, that is, for normal parameters passed using standard mechanisms and locations as defined in this calling standard. For all other cases, the signature information will be null so that an attempted call between native and translated code will fail.

Figure 5-2 I64 Signature Information Block (PSIG)

5.2.3 Signature Information Block Content

The content of Alpha and I64 signature information blocks is described in Table 5-2, Table 5-3, and Table 5-4. Table 5-2 omits reference to particular bit positions. In these tables and subsequence sections, the following logical names are used to refer to corresponding Alpha and Intel Itanium registers:

Name Interpretation Alpha Register Itanium Register

RetVal First (or only) integer return register R0 R8

RetVal2 Second integer return register R1 R9

RetFlt First (or only) floating-point return register F0 F8 for S_ and T_floating
R8 for F_, D_ and G_floating

RetFlt2 Second floating-point return register F1 F9 for S_ and T_floating
R9 for F_, D_ and G_floating

Name	Interpretation	Alpha Register	Itanium Register
RetVal	First (or only) integer return register	R0	R8
RetVal2	Second integer return register	R1	R9
RetFlt	First (or only) floating-point return register	F0	F8 for S_ and T_floating R8 for F_, D_ and G_floating
RetFlt2	Second floating-point return register	F1	F9 for S_ and T_floating R9 for F_, D_ and G_floating

Table 5-2 Contents of the Signature Information Block (PSIG)
Field Name Contents

PSIG$V_CTRL (I64 systems only) A 3-bit control information field. Not used in a signature information block. Contents are unspecified. Allows a signature information block to occur as an immediate value in the signature information field of a function descriptor (see Section 5.1.3).

PSIG$V_X (I64 systems only) A 5-bit unused field. Must be zero.

PSIG$V_FUNC_RETURN A 4-bit field that describes which registers are used for the function value return (if there is one) and what format is used for those registers.
Table 5-4 lists and describes the possible encoded values of PSIG$V_FUNC_RETURN.

PSIG$V_REG_ARG_INFO A field that is divided into groups of 4 bits that correspond to the arguments that can be passed in registers. There are six groups for a total of 24 bits on Alpha systems and eight groups for a total of 32 bits on I64 systems. The first group (lowest order bits) describes the first register argument, the second group (next lowest order bits) describes the second register argument, and so on. Table 5-3 lists the possible codes.

PSIG$V_SUMMARY A 4-bit field that contains coded argument signature information as follows:

Bit Name Meaning

0, 1 PSIG$M_SU_ASUM On Alpha, summary of arguments 7 through PSIG$B_ARG_COUNT.
On Itanium, summary of arguments 9 through PSIG$B_ARG_COUNT:
00 = All arguments are 64-bit or not used
01 = All arguments are 32-bit sign extended or not used
10 = Reserved
11 = Other (not 00 or 01)

2 PSIG$M_SU_VLIST VAX formatted argument list expected

3 Must be 0 (reserved)

PSIG$M_SU_ASUM values of 00 and 01 (binary) allow a quick test for the occurrence of either an all 32-bit or an all 64-bit argument list. The values for the PSIG$V_MEMORY_ARG_INFO field must be valid even when these occurrences apply.

PSIG$B_ARG_COUNT Unsigned byte (bits 0--7) that specifies the number of 64-bit argument items described in the argument signature information. This count includes the initial arguments that are passed in registers.

PSIG$V_MEMORY_ARG_INFO Array of 2-bit values that describe each of the arguments through PSIG$B_ARG_COUNT that are passed in memory (rather than registers). PSIG$S_MEMORY_ARG_INFO data is only defined for the arguments described by PSIG$B_ARG_COUNT. These memory argument signature bits are defined as follows:

Value Name Meaning¹

0 MASE$K_MA_Q 64-bit argument

1 Reserved

2 MASE$K_MA_I32 32-bit sign-extended argument

3 Reserved

¹For a more detailed description of these conversions, see Section 5.2.4.
²The X_floating and X_floating complex data types do not appear in this table because these types are not passed using the by value mechanism (see Section 3.7.5.1).

Table 5-3 Register Argument Signature Encodings
Value Name Meaning^1,2

0 RASE$K_RA_NOARG Argument is not present

1 RASE$K_RA_Q 64-bit argument passed in an integer register

2 RASE$K_RA_I32 32-bit argument sign extended to 64 bits passed in an integer register

3 RASE$K_RA_U32 32-bit unsigned argument zero extended to 64 bits passed in an integer register

4 RASE$K_RA_FF F_floating argument passed in a floating-point register on Alpha or a general register on I64 systems

5 RASE$K_RA_FD D_floating argument passed in a floating-point register on Alpha or a general register on I64 systems

6 RASE$K_RA_FG G_floating argument passed in a floating-point register on Alpha or a general register on I64 systems

7 RASE$K_RA_FS S_floating argument passed in a floating-point register

8 RASE$K_RA_FT T_floating argument passed in a floating-point register

9--15 Reserved for future use

**Table 5-3 Register Argument Signature Encodings**
Value	Name	Meaning^1,2
0	RASE$K_RA_NOARG	Argument is not present
1	RASE$K_RA_Q	64-bit argument passed in an integer register
2	RASE$K_RA_I32	32-bit argument sign extended to 64 bits passed in an integer register
3	RASE$K_RA_U32	32-bit unsigned argument zero extended to 64 bits passed in an integer register
4	RASE$K_RA_FF	F_floating argument passed in a floating-point register on Alpha or a general register on I64 systems
5	RASE$K_RA_FD	D_floating argument passed in a floating-point register on Alpha or a general register on I64 systems
6	RASE$K_RA_FG	G_floating argument passed in a floating-point register on Alpha or a general register on I64 systems
7	RASE$K_RA_FS	S_floating argument passed in a floating-point register
8	RASE$K_RA_FT	T_floating argument passed in a floating-point register
9--15		Reserved for future use

Table 5-4 Function Return Signature Encodings
Value Name Meaning^1,2

0 PSIG$K_FR_I64 64-bit result in RetVal
or No function result provided
or First parameter mechanism used

1 PSIG$K_FR_D64 64-bit result with low 32 bits sign extended in RetVal and high 32 bits sign extended in RetVal2

2 PSIG$K_FR_I32 32-bit sign extended to 64-bit result in RetVal

3 PSIG$K_FR_U32 32-bit unsigned result (zero extended) in RetVal

4 PSIG$K_FR_FF F_floating result in RetFlt

5 PSIG$K_FR_FD D_floating result in RetFlt

6 PSIG$K_FR_FG G_floating result in RetFlt

7 PSIG$K_FR_FS S_floating result in RetFlt

8 PSIG$K_FR_FT T_floating result in RetFlt

9, 10 Reserved for future use

11 PSIG$K_FR_FFC F_floating complex result in RetFlt and RetFlt2

12 PSIG$K_FR_FDC D_floating complex result in RetFlt and RetFlt2

13 PSIG$K_FR_FGC G_floating complex result in RetFlt and RetFlt2

14 PSIG$K_FR_FSC S_floating complex result in RetFlt and RetFlt2

15 PSIG$K_FR_FTC T_floating complex result in RetFlt and RetFlt2

**Table 5-4 Function Return Signature Encodings**
Value	Name	Meaning^1,2
0	PSIG$K_FR_I64	64-bit result in RetVal or No function result provided or First parameter mechanism used
1	PSIG$K_FR_D64	64-bit result with low 32 bits sign extended in RetVal and high 32 bits sign extended in RetVal2
2	PSIG$K_FR_I32	32-bit sign extended to 64-bit result in RetVal
3	PSIG$K_FR_U32	32-bit unsigned result (zero extended) in RetVal
4	PSIG$K_FR_FF	F_floating result in RetFlt
5	PSIG$K_FR_FD	D_floating result in RetFlt
6	PSIG$K_FR_FG	G_floating result in RetFlt
7	PSIG$K_FR_FS	S_floating result in RetFlt
8	PSIG$K_FR_FT	T_floating result in RetFlt
9, 10		Reserved for future use
11	PSIG$K_FR_FFC	F_floating complex result in RetFlt and RetFlt2
12	PSIG$K_FR_FDC	D_floating complex result in RetFlt and RetFlt2
13	PSIG$K_FR_FGC	G_floating complex result in RetFlt and RetFlt2
14	PSIG$K_FR_FSC	S_floating complex result in RetFlt and RetFlt2
15	PSIG$K_FR_FTC	T_floating complex result in RetFlt and RetFlt2

5.2.4 Call Parameter PSIG Conversions

Note that for the purposes of translated images, an address on OpenVMS Alpha or I64 is described using RASE$K_RA_I32 or MASE$K_MA_I32 as appropriate.

5.2.4.1 Native-Alpha-to-Translated-VAX PSIG Conversions

A detailed description of the native-to-translated call conversions for the PSIG$V_REG_ARG_INFO and the PSIG$V_FUNC_RETURN field values is given in Table 5-5.

Table 5-5 Native-to-Translated Conversion of the PSIG Field Values
Name Description

PSIG$V_REG_ARG_INFO Field Conversions

RASE$K_RA_Q The low-order 32 bits of the native integer register contents are used to fill the first of two longword entries in the VAX formatted argument list, while the high-order 32 bits are used to fill the second longword entry. This counts as two arguments in the VAX formatted argument list.

RASE$K_RA_I32
RASE$K_RA_U32 The low-order 32 bits of the integer register contents are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. The high-order 32 bits are ignored. This counts as one argument in the VAX formatted argument list.

RASE$K_RA_FF The single-precision contents of a floating-point register are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. This counts as one argument in the VAX formatted argument list. The Alpha store instruction STF (or an equivalent sequence on Itanium systems) is used to place the register contents into memory.

RASE$K_RA_FD
RASE$K_RA_FG The double-precision contents of a floating-point register are used to fill two longword entries in the VAX formatted argument list passed to the translated procedure. This counts as two arguments in the VAX formatted argument list. The Alpha store instruction STG (or an equivalent sequence on Itanium systems) is used to place the register contents into memory.

RASE$K_RA_FS
RASE$K_RA_FT Undefined.

PSIG$V_MEMORY_ARG_INFO Field Conversions

MASE$K_MA_Q
MASE$K_MA_I32 These convert like the RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the native argument list entry is stored in memory (rather than in a register).

PSIG$V_FUNC_RETURN Field Conversions

PSIG$K_FR_I64 The translated code is returning a 64-bit result split between VAX R0 and R1. The low-order 32 bits of R1 are shifted left and combined with the low-order 32 bits of R0 to form the 64-bit result that is returned to the native caller in RetVal.

PSIG$K_FR_D64 The translated code is returning a 64-bit result split between VAX R0 and R1. Both R0 and R1 are sign extended from 32 to 64 bits and returned to the native caller in RetVal and RetVal2.

PSIG$K_FR_I32
PSIG$K_FR_U32 The translated code is returning a 32-bit result in VAX R0. R0 is sign extended from 32 to 64 bits and returned to the native caller in RetVal.

PSIG$K_FR_FF The single-precision contents of the result in VAX R0 is loaded into native register RetFlt.

PSIG$K_FR_FD
PSIG$K_FR_FG The double-precision contents in VAX registers R0 and R1 are combined and loaded into native register RetFlt.

PSIG$K_FR_FS
PSIG$K_FR_FT Undefined.

PSIG$K_FR_FFC The single-precision complex contents in VAX registers R0 and R1 are loaded into native registers RetFlt and RetFlt2.

PSIG$K_FR_FDC
PSIG$K_FR_FGC The translated code is returning a double-precision complex result using the hidden first parameter method (by reference). The storage for the result is allocated prior to the call and the address is passed as the extra parameter. Upon return, the result is copied from the temporary storage into the native floating-point return registers and returned to the native caller.

PSIG$K_FR_FSC
PSIG$K_FR_FTC Undefined.

**Table 5-5 Native-to-Translated Conversion of the PSIG Field Values**
Name	Description
PSIG$V_REG_ARG_INFO Field Conversions
RASE$K_RA_Q	The low-order 32 bits of the native integer register contents are used to fill the first of two longword entries in the VAX formatted argument list, while the high-order 32 bits are used to fill the second longword entry. This counts as two arguments in the VAX formatted argument list.
RASE$K_RA_I32 RASE$K_RA_U32	The low-order 32 bits of the integer register contents are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. The high-order 32 bits are ignored. This counts as one argument in the VAX formatted argument list.
RASE$K_RA_FF	The single-precision contents of a floating-point register are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. This counts as one argument in the VAX formatted argument list. The Alpha store instruction STF (or an equivalent sequence on Itanium systems) is used to place the register contents into memory.
RASE$K_RA_FD RASE$K_RA_FG	The double-precision contents of a floating-point register are used to fill two longword entries in the VAX formatted argument list passed to the translated procedure. This counts as two arguments in the VAX formatted argument list. The Alpha store instruction STG (or an equivalent sequence on Itanium systems) is used to place the register contents into memory.
RASE$K_RA_FS RASE$K_RA_FT	Undefined.
PSIG$V_MEMORY_ARG_INFO Field Conversions
MASE$K_MA_Q MASE$K_MA_I32	These convert like the RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the native argument list entry is stored in memory (rather than in a register).
PSIG$V_FUNC_RETURN Field Conversions
PSIG$K_FR_I64	The translated code is returning a 64-bit result split between VAX R0 and R1. The low-order 32 bits of R1 are shifted left and combined with the low-order 32 bits of R0 to form the 64-bit result that is returned to the native caller in RetVal.
PSIG$K_FR_D64	The translated code is returning a 64-bit result split between VAX R0 and R1. Both R0 and R1 are sign extended from 32 to 64 bits and returned to the native caller in RetVal and RetVal2.
PSIG$K_FR_I32 PSIG$K_FR_U32	The translated code is returning a 32-bit result in VAX R0. R0 is sign extended from 32 to 64 bits and returned to the native caller in RetVal.
PSIG$K_FR_FF	The single-precision contents of the result in VAX R0 is loaded into native register RetFlt.
PSIG$K_FR_FD PSIG$K_FR_FG	The double-precision contents in VAX registers R0 and R1 are combined and loaded into native register RetFlt.
PSIG$K_FR_FS PSIG$K_FR_FT	Undefined.
PSIG$K_FR_FFC	The single-precision complex contents in VAX registers R0 and R1 are loaded into native registers RetFlt and RetFlt2.
PSIG$K_FR_FDC PSIG$K_FR_FGC	The translated code is returning a double-precision complex result using the hidden first parameter method (by reference). The storage for the result is allocated prior to the call and the address is passed as the extra parameter. Upon return, the result is copied from the temporary storage into the native floating-point return registers and returned to the native caller.
PSIG$K_FR_FSC PSIG$K_FR_FTC	Undefined.

In all 64-bit cases, the longword at the lower memory address forms the earlier argument in the VAX formatted argument list. Also, for single-precision floating-point types, the unused 32 bits of an native 64-bit argument list entry are undefined.

5.2.4.2 Translated-VAX-to-Native-Alpha PSIG Conversions

A detailed description of the translated-to-native call conversions for the PSIG$V_REG_ARG_INFO and the PSIG$V_FUNC_RETURN field values is given in Table 5-6.

Table 5-6 Translated-to-Native Conversion of the PSIG Field Values
Name Description

PSIG$V_REG_ARG_INFO Field Conversions

RASE$K_RA_Q The contents of two successive longwords from the VAX formatted argument list are combined to form a single quadword value that is placed in an integer register. This counts as one argument in the native argument list.

RASE$K_RA_I32
RASE$K_RA_U32 The contents of one longword entry from the VAX formatted argument list is sign extended and placed in the integer register. This counts as one argument in the native argument list.

RASE$K_RA_FF A single longword entry from the VAX formatted argument list is used to form a floating-point value in a floating-point register. This counts as one argument in the native argument list. The Alpha load instruction LDF (or an equivalent sequence on I64 systems) is used to place the argument in the floating-point register.

RASE$K_RA_FD
RASE$K_RA_FG Two longword entries from the VAX formatted argument list are combined to form a single floating-point value in a floating-point register. This counts as one argument in the native argument list. The Alpha load instruction LDG (or an equivalent sequence on I64 systems) is used to place the argument in the floating-point register.

RASE$K_RA_FS
RASE$K_RA_FT Undefined.

PSIG$V_MEMORY_ARG_INFO Field Conversions

MASE$K_MA_Q
MASE$K_MA_I32 These convert like RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the native argument list entry is stored in memory (rather than a register). ¹

PSIG$V_FUNC_RETURN Field Conversions

PSIG$K_FR_I64 The native code is returning a 64-bit result in RetVal. The high 32 bits of RetVal are moved to the VAX R1 register and the low 32 bits of RetVal are moved to the VAX R0 register. The 64-bit result is then returned to the translated caller in VAX R0 and R1.

PSIG$K_FR_D64 The native code is returning a 64-bit result split between RetVal and RetVal2. Both are returned to the translated caller in place.

PSIG$K_FR_I32
PSIG$K_FR_U32 The native code is returning a 32-bit result in RetVal. The low 32 bits of RetVal are returned to the translated caller.

PSIG$K_FR_FF The single-precision result in native register RetFlt is returned in the VAX register R0. ¹

PSIG$K_FR_FD
PSIG$K_FR_FG The double-precision result in native register RetFlt is returned in VAX registers R0 and R1.

PSIG$K_FR_FS
PSIG$K_FR_FT Undefined.

PSIG$K_FR_FFC The single-precision complex result in native registers RetFlt and RetFlt2 is returned in the VAX registers R0 and R1. ¹

PSIG$K_FR_FDC
PSIG$K_FR_FGC The native code is returning a double-precision complex result in the native floating-point registers. The result is copied into the storage given by the hidden first parameter passed by the translated caller.

PSIG$K_FR_FSC
PSIG$K_FR_FTC Undefined.

**Table 5-6 Translated-to-Native Conversion of the PSIG Field Values**
Name	Description
PSIG$V_REG_ARG_INFO Field Conversions
RASE$K_RA_Q	The contents of two successive longwords from the VAX formatted argument list are combined to form a single quadword value that is placed in an integer register. This counts as one argument in the native argument list.
RASE$K_RA_I32 RASE$K_RA_U32	The contents of one longword entry from the VAX formatted argument list is sign extended and placed in the integer register. This counts as one argument in the native argument list.
RASE$K_RA_FF	A single longword entry from the VAX formatted argument list is used to form a floating-point value in a floating-point register. This counts as one argument in the native argument list. The Alpha load instruction LDF (or an equivalent sequence on I64 systems) is used to place the argument in the floating-point register.
RASE$K_RA_FD RASE$K_RA_FG	Two longword entries from the VAX formatted argument list are combined to form a single floating-point value in a floating-point register. This counts as one argument in the native argument list. The Alpha load instruction LDG (or an equivalent sequence on I64 systems) is used to place the argument in the floating-point register.
RASE$K_RA_FS RASE$K_RA_FT	Undefined.
PSIG$V_MEMORY_ARG_INFO Field Conversions
MASE$K_MA_Q MASE$K_MA_I32	These convert like RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the native argument list entry is stored in memory (rather than a register). ¹
PSIG$V_FUNC_RETURN Field Conversions
PSIG$K_FR_I64	The native code is returning a 64-bit result in RetVal. The high 32 bits of RetVal are moved to the VAX R1 register and the low 32 bits of RetVal are moved to the VAX R0 register. The 64-bit result is then returned to the translated caller in VAX R0 and R1.
PSIG$K_FR_D64	The native code is returning a 64-bit result split between RetVal and RetVal2. Both are returned to the translated caller in place.
PSIG$K_FR_I32 PSIG$K_FR_U32	The native code is returning a 32-bit result in RetVal. The low 32 bits of RetVal are returned to the translated caller.
PSIG$K_FR_FF	The single-precision result in native register RetFlt is returned in the VAX register R0. ¹
PSIG$K_FR_FD PSIG$K_FR_FG	The double-precision result in native register RetFlt is returned in VAX registers R0 and R1.
PSIG$K_FR_FS PSIG$K_FR_FT	Undefined.
PSIG$K_FR_FFC	The single-precision complex result in native registers RetFlt and RetFlt2 is returned in the VAX registers R0 and R1. ¹
PSIG$K_FR_FDC PSIG$K_FR_FGC	The native code is returning a double-precision complex result in the native floating-point registers. The result is copied into the storage given by the hidden first parameter passed by the translated caller.
PSIG$K_FR_FSC PSIG$K_FR_FTC	Undefined.

¹Note that for single-precision floating-point types, the unused 32 bits of a native 64-bit argument list entry are undefined.

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