HP OpenVMS Debugger Manual

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4.4.2 Examing and Depositing into Alpha Registers

On Alpha processors, the Alpha architecture provides 32 general (integer) registers and 32 floating-point registers, some of which are used for temporary address and data storage. Table 4-2 identifies the debugger built-in symbols that refer to Alpha registers.

Table 4-2 Debugger Symbols for Alpha Registers
Symbol Description

Alpha Integer Registers

%R0...%R28 Registers R0...R28

%FP (%R29) Stack frame base register (FP)

%SP (%R30) Stack pointer (SP)

%R31 ReadAsZero/Sink (RZ)

%PC Program counter (PC)

%PS Processor status register (PS). The built-in symbols %PSL and %PSW are disabled for Alpha processors.

Alpha Floating-Point Registers

%F0...%F30 Registers F0...F30

%F31 ReadAsZero/Sink

**Table 4-2 Debugger Symbols for Alpha Registers**
Symbol	Description
Alpha Integer Registers
%R0...%R28	Registers R0...R28
%FP (%R29)	Stack frame base register (FP)
%SP (%R30)	Stack pointer (SP)
%R31	ReadAsZero/Sink (RZ)
%PC	Program counter (PC)
%PS	Processor status register (PS). The built-in symbols %PSL and %PSW are disabled for Alpha processors.
Alpha Floating-Point Registers
%F0...%F30	Registers F0...F30
%F31	ReadAsZero/Sink

On Alpha processors:

You can omit the percent sign (%) prefix if your program has not declared a symbol with the same name.
You cannot deposit a value into register R30.
You cannot deposit a value into registers R31 or F31. They are permanently assigned the value 0.
There are no vector registers.

The following examples show how to examine and deposit into registers:

DBG> SHOW TYPE ! Show type for locations without type: long integer ! a compiler-generated type. DBG> SHOW RADIX ! Identify current radix. input radix: decimal output radix: decimal DBG> EXAMINE %R11 ! Display value in R11. MOD3\%R11: 1024 DBG> DEPOSIT %R11 = 444 ! Deposit new value into R11. DBG> EXAMINE %R11 ! Check new value. R11: 444 DBG> EXAMINE %PC ! Display value in program counter. MOD\%PC: 1553 DBG> EXAMINE %SP ! Display value in stack pointer. 0\%SP: 2147278720 DBG>

See Section 4.3.1 for specific information about the PC.

Processor Status (Alpha Only)

On Alpha processors, the processor status (PS) is a register whose value represents a number of processor state variables. The first three bits of the PS are reserved for the use of the software. The values of these bits can be controlled by a user program. The remainder of the bits, bits 4 to 64, contain privileged information and cannot be altered by a user-mode program.

The following example shows how to examine the contents of the PS:

DBG> EXAMINE %PS MOD1\%PS: SP_ALIGN IPL VMM CM IP SW 48 0 0 USER 0 3 DBG>

See the Alpha Architecture Reference Manual for complete information about the PS, including the values of the various bits.

You can also display the information in the PS in other formats. For example:

DBG> EXAMINE/LONG/HEX %PS MOD1\%PS: 0000001B DBG> EXAMINE/LONG/BIN %PS MOD1\%PS: 00000000 00000000 00000000 00011011 DBG>

The command EXAMINE/PS displays the value at any location in PS format. This is useful for examining the combined current and saved PS values.

4.4.3 Examing and Depositing into I64 Registers

On I64 processors, the I64 architecture provides:

Up to 128 64-bit general registers
Up to 128 82-bit floating-point registers (the debugger allows you to treat these as full octawords),
Up to 64 1-bit predicate, 8 64-bit branch, and 128 (only 20 are accessible/used) application registers
Special registers (for example, %PC) and viritual registers (for example, %RETURN_PC)

Most of these registers are read/writable from user mode debug. Some, however, are not writable and others are only accessible from the higher privleges related with the System Code Debugger (SCD) configuration (see HP OpenVMS System Analysis Tools Manual).

TABLE_ROW>(%BSP (%AR17)\ Backing Store Pointer )
Table 4-3 Debugger Symbols for I64 Registers
Symbol Description

I64 Application Registers

%KR0...%KR7 Kernel registers 0...7

%RSC (%AR16) Register Stack Configuration

%BSPSTORE (%AR18) Backing Store Pointer for Memory Stores

%RNAT (%AR19) RSE NaT Collection

%CCV ($AR32) Compare and Exchange Compare Value

%UNAT (%AR36) User NaT Collection

%FPSR (%AR40) Floating-point Status

%PFS (%AR64) Previous Function State

%LC (%AR65) Loop Count

%EC (%AR66) Epilog Count

%CSD Code Segment

%SSD Stack Segment

Control Registers

%DCR (%CR0) Default Control

%ITM (%CR1) Interval Timer Match (only visible for SCD)

%IVA (%CR2) Interruption Vector Address (only visible for SCD)

%PTA (%CR8) Page Table Address (only visible for SCD)

%PSR (%CR9, %ISPR) Interruption Processor Status

%ISR (%CR17) Interruption Status

%IIP (%CR19) Interruption Instruction Pointer

%IFA (%CR20) Interruption Faulting Address

%ITIR (%CR21) Interruption TLB Insertion

%IIPA (%CR22) Interruption Instruction Previous

%IFS (%CR23) Interruption Function State

%IIM (%CR24) Interruption Immediate

%IHA (%CR25) Interruption Hash Address

%LID (%CR64) Local Interrupt ID (only visible for SCD)

%TPR (%CR66) Task Priority (only visible for SCD)

%IRR0...%IRR3 (%CR68...%CR71) External Interrupt Request 0...3 (only visible for SCD)

%ITV (%CR72) Interval Timer (only visible for SCD)

%PMV (%CR73) Performance Monitoring (only visible for SCD)

%CMCV (%CR74) Corrected Machine Check Vector (only visible for SCD)

%IRR0 and %IRR1 (%CR80 and %CR81) Local Redirection 0:1 (only visible for SCD)

Special Registers

%IH (%SR0) Invocation Handle

%PREV_BSP Previous Backing Store Pointer

%PC (%IP) Program Counter (Instruction Pointer | slot number)

%RETURN_PC Return Program Counter

%CFM Current Frame Marker

%NEXT_PFS Next Prefious Frame State

%PSP Previous Stack Pointer

%CHFCTX_ADDR Condition Handling Facility Context Address

%OSSD Operating System Specific Data

%HANDLER_FV Handler Function Value

%LSDA Language Specific Data Area

%UM User Mask

Predicate Registers

%PR (%PRED) Predicate Collection Register---Collection of %P0...%P63

%P0...%P63 Predicate (single-bit)Registers 0...63

Branch Registers

%RP (%B0) Return Pointer

%B1...%B7 Branch Registers 1...7

General Integer Registers

%R0 General Integer Register 0

%GP (%R1) Global Data Pointer

%R2...%R11 General Integer Registers 2...11

%SP (%R12) Stack Pointer

%TP (%R13) Thread Pointer

%R14...%R24 General Integer Registers 14...24

%AP (%R25) Argument Information

%R26...%R127 General Integer Registers 26...127

Output Registers

%OUT0...%OUT7 Output Registers, runtime aliases (i.e., If the frame has allocated output registers, then %OUT0 maps to the first allocated output registers, for example, %R38, etc.)

General Registers

%GRNAT0 and %GRNAT1 General Register Not A Thing (NAT) collection registers 64 bits each, for example, %GRNAT0<3,1,0> is the NAT bit for %R3.

Floating Point Registers

%F0...%F127 Floating Poing Registers 0...127

**Table 4-3 Debugger Symbols for I64 Registers**
Symbol	Description
I64 Application Registers
%KR0...%KR7	Kernel registers 0...7
%RSC (%AR16)	Register Stack Configuration
%BSPSTORE (%AR18)	Backing Store Pointer for Memory Stores
%RNAT (%AR19)	RSE NaT Collection
%CCV ($AR32)	Compare and Exchange Compare Value
%UNAT (%AR36)	User NaT Collection
%FPSR (%AR40)	Floating-point Status
%PFS (%AR64)	Previous Function State
%LC (%AR65)	Loop Count
%EC (%AR66)	Epilog Count
%CSD	Code Segment
%SSD	Stack Segment
Control Registers
%DCR (%CR0)	Default Control
%ITM (%CR1)	Interval Timer Match (only visible for SCD)
%IVA (%CR2)	Interruption Vector Address (only visible for SCD)
%PTA (%CR8)	Page Table Address (only visible for SCD)
%PSR (%CR9, %ISPR)	Interruption Processor Status
%ISR (%CR17)	Interruption Status
%IIP (%CR19)	Interruption Instruction Pointer
%IFA (%CR20)	Interruption Faulting Address
%ITIR (%CR21)	Interruption TLB Insertion
%IIPA (%CR22)	Interruption Instruction Previous
%IFS (%CR23)	Interruption Function State
%IIM (%CR24)	Interruption Immediate
%IHA (%CR25)	Interruption Hash Address
%LID (%CR64)	Local Interrupt ID (only visible for SCD)
%TPR (%CR66)	Task Priority (only visible for SCD)
%IRR0...%IRR3 (%CR68...%CR71)	External Interrupt Request 0...3 (only visible for SCD)
%ITV (%CR72)	Interval Timer (only visible for SCD)
%PMV (%CR73)	Performance Monitoring (only visible for SCD)
%CMCV (%CR74)	Corrected Machine Check Vector (only visible for SCD)
%IRR0 and %IRR1 (%CR80 and %CR81)	Local Redirection 0:1 (only visible for SCD)
Special Registers
%IH (%SR0)	Invocation Handle
%PREV_BSP	Previous Backing Store Pointer
%PC (%IP)	Program Counter (Instruction Pointer \| slot number)
%RETURN_PC	Return Program Counter
%CFM	Current Frame Marker
%NEXT_PFS	Next Prefious Frame State
%PSP	Previous Stack Pointer
%CHFCTX_ADDR	Condition Handling Facility Context Address
%OSSD	Operating System Specific Data
%HANDLER_FV	Handler Function Value
%LSDA	Language Specific Data Area
%UM	User Mask
Predicate Registers
%PR (%PRED)	Predicate Collection Register---Collection of %P0...%P63
%P0...%P63	Predicate (single-bit)Registers 0...63
Branch Registers
%RP (%B0)	Return Pointer
%B1...%B7	Branch Registers 1...7
General Integer Registers
%R0	General Integer Register 0
%GP (%R1)	Global Data Pointer
%R2...%R11	General Integer Registers 2...11
%SP (%R12)	Stack Pointer
%TP (%R13)	Thread Pointer
%R14...%R24	General Integer Registers 14...24
%AP (%R25)	Argument Information
%R26...%R127	General Integer Registers 26...127
Output Registers
%OUT0...%OUT7	Output Registers, runtime aliases (i.e., If the frame has allocated output registers, then %OUT0 maps to the first allocated output registers, for example, %R38, etc.)
General Registers
%GRNAT0 and %GRNAT1	General Register Not A Thing (NAT) collection registers 64 bits each, for example, %GRNAT0<3,1,0> is the NAT bit for %R3.
Floating Point Registers
%F0...%F127	Floating Poing Registers 0...127

On I64 processors:

You can omit the percent sign (%) prefix if your program has not declared a symbol with the same name.
You cannot deposit values into the following kinds of registers: unallocated, disabled, or unreadable registers. For example:
- %R38 to %R127, if only %R32 to %R37 were allocated
- %F0 (always 0.0)
- %F1 (always 1.0)
- %R0 (always 0)
- %SP
- %P0 (always 1)
- %GRNAT0 and %GRNAT1
- All of the special registers, except %PC
- Most of the control and application registers (see below)
For regular user mode debug and SCD, you can also deposit into registers, as follows:
- Control registers %IPSR, %ISR, %IIP, %IFA, %ITIR, %IIPA, %IFS, %IIM, and %IHA for exception frames
- Application registers %RSC and %CCV
For SCD ONLY, you can also deposit into registers, as follows:
- Application registers %KR0 to %KR7
- Control registers %DCR, %ITM, %IVA, %PTA, %LID, %TPR, %IRR0 to %IRR3, %ITV, %PMV, %CMCV, %LRR0, and %LRR1
There are no vector registers.
Some register reads are automatically formatted. You can override this formating, as shown in Section 4.4.2 (for example, EXAMINE/QUAD/HEX %FPSR).

For information on the Floating Point Status Register (%FPSR), see the Intel IA-64 Architecture Sofware Developer's Manual Volume 1. Example:

DBG> ex %fpsr LOOPER\main\%FPSR: I U O Z D V TD RC PC WRE FTZ SF3 0 0 0 0 0 0 1 0 3 0 0 SF2 0 0 0 0 0 0 1 0 3 0 0 SF1 0 0 0 0 0 0 1 0 3 1 0 SF0 0 0 0 0 0 0 0 0 3 0 0 TRAPS ID UD OD ZD DD VD 1 1 1 1 1 1 DBG>

You can also force this formatting on any location (see EXAMINE/FPSR).

For information about Previous Function State (%PFS), Current Frame Maker (%CFM), Interrtupt Function State (%IFS), and Next Previous Function State (%NEXT_PFS) registers, see Intel IA-64 Architecture Sofware Developer's Manual, Volume 1. Example:

DBG> ex %pfs LOOPER\main\%PFS: PPL PEC SOF SOL SOR RRB_GR RRB_FR RRB_PR 3 0 29 21 0 0 0 0 DBG> ex %cfm LOOPER\main\%CFM: SOF SOL SOR RRB_GR RRB_FR RRB_PR 6 5 0 0 0 0 DBG> ex %ifs LOOPER\main\%IFS: SOF SOL SOR RRB_GR RRB_FR RRB_PR 6 5 0 0 0 0 DBG> ex %next_pfs LOOPER\main\%NEXT_PFS: PPL PEC SOF SOL SOR RRB_GR RRB_FR RRB_PR 3 0 6 5 0 0 0 0 DBG>

Also see EXAMINE/PFS and EXAMINE/CFM.

For information about the Process Status Register (%PSR), see the Intel IA-64 Architecture Sofware Developer's Manual, Volume 2. Example:

DBG> ex %psr LOOPER\main\%PSR: IA BN ED RI SS DD DA ID IT MC IS CPL RT TB LP DB SI DI PP SP DFH DFL 0 1 0 0 0 0 0 0 1 0 0 3 1 0 0 0 0 1 0 0 0 0 DT PK I IC MFH MFL AC UP BE 1 0 1 1 1 1 0 0 0 DBG>

Also see EXAMINE/PSR.

The debugger defaults to a bit vector format for the %GRNAT0, %GRANT1, and %PR registers. For example:

DBG> ex %grnat0,%pr LOOPER\main\%GRNAT0: 11111111 11111111 11111111 11000000 00000000 00000000 00000000 00000000 LOOPER\main\%PR: 00000000 00000000 00000000 00000000 11111111 01010110 10010110 10100011 DBG>

The debugger defaults to single bits for registers %p0...%p63. For example:

DBG> ex %p6,%p7 LOOPER\main\%P6: 0 LOOPER\main\%P7: 1 DBG>

4.5 Specifying a Type When Examining and Depositing

The preceding sections explain how to use the EXAMINE and DEPOSIT commands with program locations that have a symbolic name and, therefore, are associated with a compiler-generated type.

Section 4.5.1 describes how the debugger formats (types) data for program locations that do not have a symbolic name and explains how you can control the type for those locations.

Section 4.5.2 explains how to override the type associated with any program location, including a location that has a symbolic name.

4.5.1 Defining a Type for Locations Without a Symbolic Name

Program locations that do not have a symbolic name and, therefore, are not associated with a compiler-generated type have the type longword integer by default. Section 4.1.5 explains how to examine and deposit into such locations using the default type.

The SET TYPE command enables you to change the default type in order to examine and display the contents of a location in another type, or to deposit a value of one type into a location associated with another type. Table 4-4 lists the type keywords for the SET TYPE command.

Table 4-4 SET TYPE Keywords
ASCIC D_FLOAT H_FLOAT ¹ PACKED

ASCID DATE_TIME INSTRUCTION QUADWORD

ASCII: n EXTENDED_FLOAT ² LONG_FLOAT ² S_FLOAT ²

ASCIW F_LOAT LONG_LONG_FLOAT ² T_FLOAT ²

ASCIZ FLOAT LONGWORD TYPE=( type-expression)

BYTE G_FLOAT OCTAWORD WORD

X_FLOAT ²

**Table 4-4 SET TYPE Keywords**
ASCIC	D_FLOAT	H_FLOAT ¹	PACKED
ASCID	DATE_TIME	INSTRUCTION	QUADWORD
ASCII: n	EXTENDED_FLOAT ²	LONG_FLOAT ²	S_FLOAT ²
ASCIW	F_LOAT	LONG_LONG_FLOAT ²	T_FLOAT ²
ASCIZ	FLOAT	LONGWORD	TYPE=( type-expression)
BYTE	G_FLOAT	OCTAWORD	WORD
			X_FLOAT ²

¹VAX specific
²I64 and Alpha specific

For example, the following commands set the type for locations without a symbolic name to, respectively, byte integer, G_floating, and ASCII with 6 bytes of ASCII data. Each successive SET TYPE command resets the type.

DBG> SET TYPE BYTE DBG> SET TYPE G_FLOAT DBG> SET TYPE ASCII:6

Note that the SET TYPE command, when used without the /OVERRIDE qualifier, does not affect the type for program locations that have a symbolic name (locations associated with a compiler-generated type).

The SHOW TYPE command identifies the current type for locations without a symbolic name. To restore the default type for such locations, enter the SET TYPE LONGWORD command.

4.5.2 Overriding the Current Type

The SET TYPE/OVERRIDE command enables you to change the type associated with any program location, including locations with compiler-generated types. For example, after the following command is executed, an unqualified EXAMINE command displays the contents of only the first byte of the location specified and interprets the contents as byte integer data. An unqualified DEPOSIT command modifies only the first byte of the location specified and formats the data deposited as byte integer data.

DBG> SET TYPE/OVERRIDE BYTE

See Table 4-4 for the valid type keywords for the SET TYPE/OVERRIDE command.

To identify the current override type, enter the SHOW TYPE/OVERRIDE command. To cancel the current override type and restore the normal interpretation of locations that have a symbolic name, enter the CANCEL TYPE/OVERRIDE command.

The EXAMINE and DEPOSIT commands have qualifiers that enable you to override the type currently associated with a program location for the duration of the EXAMINE or DEPOSIT command. These qualifiers override any previous SET TYPE or SET TYPE/OVERRIDE command as well as any compiler-generated type. See the DEPOSIT and EXAMINE commands for the type qualifiers available to each command.

When used with a type qualifier, the EXAMINE command displays the entity specified by the address expression in that type. For example:

DBG> EXAMINE/BYTE . ! Type is byte integer. MOD3\%LINE 15 : -48 DBG> EXAMINE/WORD . ! Type is word integer. MOD3\%LINE 15 : 464 DBG> EXAMINE/LONG . ! Type is longword integer. MOD3\%LINE 15 : 749404624 DBG> EXAMINE/QUAD . ! Type is quadword integer. MOD3%LINE 15 : +0130653502894178768 DBG> EXAMINE/FLOAT . ! Type is F_floating. MOD3%LINE 15 : 1.9117807E-38 DBG> EXAMINE/G_FLOAT . ! Type is G_floating. MOD3%LINE 15 : 1.509506018605227E-300 DBG> EXAMINE/ASCII . ! Type is ASCII string. MOD3\%LINE 15 : ".." DBG>

When used with a type qualifier, the DEPOSIT command deposits a value of that type into the location specified by the address expression, which overrides the type associated with the address expression.

The remaining sections provide examples of specifying integer, string, and user-declared types with type qualifiers and the SET TYPE command.

4.5.2.1 Integer Types

The following examples show the use of the EXAMINE and DEPOSIT commands with integer-type qualifiers (/BYTE, /WORD, /LONGWORD). These qualifiers enable you to deposit a value of a particular integer type into an arbitrary program location.

DBG> SHOW TYPE ! Show type for locations without type: long integer ! a compiler-generated type. DBG> EVALU/ADDR . ! Current location is 724. 724 DBG> DEPO/BYTE . = 1 ! Deposit the value 1 into one byte ! of memory at address 724. DBG> EXAM . ! By default, 4 bytes are examined. 724: 1280461057 DBG> EXAM/BYTE . ! Examine one byte only. 724: 1 DBG> DEPO/WORD . = 2 ! Deposit the value 2 into first two ! bytes (word) of current entity. DBG> EXAM/WORD . ! Examine a word of the current entity. 724: 2 DBG> DEPO/LONG 724 = 999 ! Deposit the value 999 into 4 bytes !(a longword) beginning at address 724. DBG> EXAM/LONG 724 ! Examine 4 bytes (longword) 724: 999 ! beginning at address 724. DBG>

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